The present invention relates to a semiconductor device, and more particularly, to a reset signal generation circuit for switching the generation timing of a reset signal between timings that are asynchronous and synchronous with a system clock signal.
A semiconductor device, such as a system LSI, includes various circuits, such as a ROM and a RAM, and also includes a reset signal generation circuit for resetting each of those circuits. The reset signal generation circuit generates a reset signal for resetting each circuit when activated or when the power supply voltage decreases.
A semiconductor device, such as a system LSI, includes a CPU, a ROM for storing programs that are executed by the CPU, a RAM for temporarily storing data, and peripheral circuits such as an I/O or a counter. When the power supply voltage of the semiconductor device becomes less than the operable voltage, the setting of an internal circuit becomes unstable. In such a case, the semiconductor device may operate abnormally or the CPU may operate erroneously. To prevent this, the reset signal generation circuit of the semiconductor device monitors the power supply voltage and generates a reset signal when the power supply voltage decreases.
A synchronous circuit, such as a RAM, may be initialized by a reset signal that is asynchronous to a system clock signal. However, if a memory, such as a RAM, is provided with an asynchronous reset signal during operation, the data stored in the memory may be lost. To maintain the stored data of the memory, such a synchronous circuit must be reset based on a reset signal that is synchronous to a system clock signal. Japanese Laid-Open Patent Publication No. 2002-108510 describes a reset circuit for generating, in a low-voltage state, a reset signal that is asynchronous to the system clock signal when the system clock signal is not generated. The reset circuit also generates a reset signal that is synchronous to the system clock signal when the system clock signal is generated.